1. Field of Invention
The present invention relates to a chip package structure and manufacturing process thereof. More particularly, the present invention relates to a chip package structure with an insulating material fabricated hard support plate therein and manufacturing process thereof.
2. Description of Related Art
Flip chip (FC) interconnect technology is a technique of joining a die and a carrier together to form a chip package. The active surface of the die normally has an array of die pads each having a bump thereon and the carrier also has a series of corresponding contacts. To assemble the die and the carrier together, the die is flipped over so that the bumps align with and form electrical or mechanical connections with corresponding contacts on the carrier so that signals from the die can be transmitted to the carrier via the bumps. Thereafter, the signals can be relayed to an external electronic device through one of the internal circuits formed within the carrier. Note that flip chip technology is particularly suitable for producing a chip package requiring a high pin count. Other advantages of a flip chip package include a capacity for reducing the area occupation of the chip package and a capacity for shortening of the average signal transmission pathway. With these advantages, it has been broadly applied to various types of chip package structures including the flip chip ball grid array (FC/BGA) and the flip chip pin grid array (FC/PGA).
FIG. 1 is a schematic cross-sectional view showing the structure of a conventional flip chip ball grid array package. As shown in FIG. 1, the chip package 100 comprises a substrate 110, a plurality of bumps 120, a die 130 and a plurality of solder balls 140. The substrate 110 has a top surface 112 and a bottom surface 114. The substrate 110 furthermore comprises a plurality of bump pads 116a and a plurality of ball pads 116b. The die 130 has an active surface 132 and a back surface 134. The active surface 112 of the die 130 broadly refers to the surface where all active devices (not shown) reside. The active surface 132 of the die 130 furthermore comprises a plurality of die pads 136 each serving as a medium for signal input or signal output from the die 130. Furthermore, the die pads 136 and the bump pads 116a are positioned to correspond with each other. The bumps 120 connect one of the die pads 136 with a corresponding bump pad 116a on the other side electrically and mechanically. The solder balls 140 are attached to the respective ball pads 116 for connecting with an external electronic device electrically and mechanically.
In the process of manufacturing a conventional chip package, all circuits within the substrate 110 and contacts 116a, 116b on the top surface 112 of the substrate 110 must be fabricated prior to attaching the die 130 onto the top surface 112 of the substrate 110. Thereafter, an underfill layer 150 is applied to fill the space between the top surface 112 of the substrate 110 and the active surface 132 of the die 130. This underfill layer 150 protects the bump pads 116a, the die pads 136 and the exposed portion of the bumps 120. Furthermore, the underfill layer 150 also buffers against thermal strain mismatch between the substrate 110 and the die 130 when subjected to heat. Thus, the die pad 136 is able to connect electrically or mechanically with an external device through the bump 120 and the bump pad 116a, the internal circuits within the substrate 110, the ball pad 116b and the solder ball 140.
To increase computational speed and lower production cost of a chip, die area and pitch between the die pads must be reduced. In other words, density of the die pads must increase. When a die having high-density die pads needs to integrate with a ball grid array (BGA) or a pin grid array (PGA) package using the flip chip technique, high-density bump pads and fine pitch circuit within the substrate must be used. In other words, with the die flipped over and attached to the top surface of the substrate, the die pad is able to extend its connection with an external device via the routing wires within the substrate and a ball or a pin at the bottom surface of the substrate.
At present, the most popular material for fabricating the substrate of a flip chip ball grid array (FC/BGA) or a flip chip pin grid array (FC/PGA) is ceramic and organic material. However, an organic substrate with dielectric layers fabricated using organic material is the most common. Note that organic substrate is deeply affected by thermal expansion of the dielectric layer. Hence, the smallest possible line width and line pitch that can be produced within the organic substrate in large quantities are 25 μm and 25 μm respectively. In addition, the largest size of a piece of uncut organic substrate is only 610×610 cm2. Yet, as the die pad density continues to increase, integrating a die having high-density die pads with a substrate to form a package at a minimum production cost is important issue.